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author | whitequark <whitequark@whitequark.org> | 2020-08-26 16:20:32 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2020-08-26 16:29:42 +0000 |
commit | 9f0892159ebb88964839ea2cb5313ef1b87c624d (patch) | |
tree | afc5f41b1f62874253621d052e4a55eb4aab5987 /tests/techmap/bug2183.ys | |
parent | 08a226c9e728557f8b8c970a3a25b55ba5fc00cf (diff) | |
download | yosys-9f0892159ebb88964839ea2cb5313ef1b87c624d.tar.gz yosys-9f0892159ebb88964839ea2cb5313ef1b87c624d.tar.bz2 yosys-9f0892159ebb88964839ea2cb5313ef1b87c624d.zip |
flatten, techmap: don't canonicalize tpl driven bits via sigmap.
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:
module foo(inout a, b);
assign a = b;
endmodule
module bar(output c);
foo f(c, 1'b0);
endmodule
Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).
This issue was introduced in 9f772eb9.
Fixes #2183.
Diffstat (limited to 'tests/techmap/bug2183.ys')
-rw-r--r-- | tests/techmap/bug2183.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/techmap/bug2183.ys b/tests/techmap/bug2183.ys new file mode 100644 index 000000000..8dd09458e --- /dev/null +++ b/tests/techmap/bug2183.ys @@ -0,0 +1,11 @@ +read_verilog <<EOT +module foo(inout a, b); + assign a = b; +endmodule +module bar(output c); + foo f(c, 1'b0); +endmodule +EOT + +hierarchy -auto-top +flatten |