flatten, techmap: don't canonicalize tpl driven bits via sigmap.

For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:

    module foo(inout a, b);
      assign a = b;
    endmodule
    module bar(output c);
      foo f(c, 1'b0);
    endmodule

Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).

This issue was introduced in 9f772eb9.

Fixes #2183.

1 files changed, 11 insertions, 0 deletions

diff --git a/tests/techmap/bug2183.ys b/tests/techmap/bug2183.ys
new file mode 100644
index 000000000..8dd09458e
--- /dev/null
+++ b/tests/techmap/bug2183.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module foo(inout a, b);
+  assign a = b;
+endmodule
+module bar(output c);
+  foo f(c, 1'b0);
+endmodule
+EOT
+
+hierarchy -auto-top
+flatten