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| author | Claire Wolf <clifford@clifford.at> | 2020-03-03 08:38:32 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-03 08:38:32 -0800 |
| commit | b597f85b13b5369398350ef4ef43b7b2521eb140 (patch) | |
| tree | 18ea3d52b5927ea1491162458e16cfcfd3280418 /tests/svtypes | |
| parent | 91892465e1af2bcb5ec348b86ba4e566b040cb12 (diff) | |
| parent | f80fe8dc22ca2b3639b7b0bbff69458addb05432 (diff) | |
| download | yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.tar.gz yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.tar.bz2 yosys-b597f85b13b5369398350ef4ef43b7b2521eb140.zip | |
Merge pull request #1718 from boqwxp/precise_locations
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
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