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| author | Clifford Wolf <clifford@clifford.at> | 2019-10-14 05:24:31 +0200 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2019-10-14 05:24:31 +0200 |
| commit | e84cedfae4211244da45ef51a84213874579117e (patch) | |
| tree | fb0a14f4c06675a7d3dbb5a1f22d386402e22d0b /tests/svtypes/typedef_memory_2.sv | |
| parent | 3c6a566d865e3d70f8793225a6d211ce3d6246a1 (diff) | |
| parent | e46e8753c84ee83f871d5ce116ce4c08dd49a031 (diff) | |
| download | yosys-e84cedfae4211244da45ef51a84213874579117e.tar.gz yosys-e84cedfae4211244da45ef51a84213874579117e.tar.bz2 yosys-e84cedfae4211244da45ef51a84213874579117e.zip | |
Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/svtypes/typedef_memory_2.sv')
| -rw-r--r-- | tests/svtypes/typedef_memory_2.sv | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv new file mode 100644 index 000000000..f3089bf55 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] nibble; + + (nibble) mem[0:15]; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule |