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author | David Shah <dave@ds0.me> | 2019-09-20 11:46:37 +0100 |
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committer | David Shah <dave@ds0.me> | 2019-10-03 09:54:14 +0100 |
commit | af25585170f87506bcc7dbe5afe0fec868290d5b (patch) | |
tree | b66b8b2c1d4bd322d6179b9acc111d512f3354da /tests/svtypes/typedef_memory_2.sv | |
parent | 30d23260309ef392a0e69fe5294c38b71ad0692e (diff) | |
download | yosys-af25585170f87506bcc7dbe5afe0fec868290d5b.tar.gz yosys-af25585170f87506bcc7dbe5afe0fec868290d5b.tar.bz2 yosys-af25585170f87506bcc7dbe5afe0fec868290d5b.zip |
sv: Add support for memories of a typedef
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/svtypes/typedef_memory_2.sv')
-rw-r--r-- | tests/svtypes/typedef_memory_2.sv | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv new file mode 100644 index 000000000..1e8abb155 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] nibble; + + nibble mem[0:15]; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule
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