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| author | Peter <peter@crozier.com> | 2020-02-27 16:59:19 +0000 |
|---|---|---|
| committer | Grazfather <grazfather@gmail.com> | 2020-03-22 18:20:46 -0700 |
| commit | 6d8d6b402fafd31ef555415b9f4b9e17941337ea (patch) | |
| tree | 54ef6f1b1e398db15338e2ac145470c3efa2bc59 /tests/svtypes/typedef_memory_2.sv | |
| parent | 14f32028ec878b8ba7324584631523f5b571b39f (diff) | |
| download | yosys-6d8d6b402fafd31ef555415b9f4b9e17941337ea.tar.gz yosys-6d8d6b402fafd31ef555415b9f4b9e17941337ea.tar.bz2 yosys-6d8d6b402fafd31ef555415b9f4b9e17941337ea.zip | |
Revert typedef tests to standard grammar.
Diffstat (limited to 'tests/svtypes/typedef_memory_2.sv')
| -rw-r--r-- | tests/svtypes/typedef_memory_2.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index f3089bf55..6d65131db 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -1,7 +1,7 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); typedef logic [3:0] nibble; - (nibble) mem[0:15]; + nibble mem[0:15]; always @(posedge clk) begin if (wen) mem[addr] <= wdata; |