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author | David Shah <dave@ds0.me> | 2019-09-20 11:39:15 +0100 |
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committer | David Shah <dave@ds0.me> | 2019-10-03 09:54:14 +0100 |
commit | 30d23260309ef392a0e69fe5294c38b71ad0692e (patch) | |
tree | 18cb44e1dfdf22c911ed889b452ccbe400edd32c /tests/svtypes/typedef_memory.sv | |
parent | e70e4afb60a41da6d9f6200b20f36f61c6b993b2 (diff) | |
download | yosys-30d23260309ef392a0e69fe5294c38b71ad0692e.tar.gz yosys-30d23260309ef392a0e69fe5294c38b71ad0692e.tar.bz2 yosys-30d23260309ef392a0e69fe5294c38b71ad0692e.zip |
sv: Add support for memory typedefs
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'tests/svtypes/typedef_memory.sv')
-rw-r--r-- | tests/svtypes/typedef_memory.sv | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv new file mode 100644 index 000000000..c848c3287 --- /dev/null +++ b/tests/svtypes/typedef_memory.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] ram16x4_t[0:15]; + + ram16x4_t mem; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule
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