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| author | clairexen <claire@symbioticeda.com> | 2020-07-01 16:40:20 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-01 16:40:20 +0200 |
| commit | 8ce4f8790ecf33f7df19e0fb54a749abe026831d (patch) | |
| tree | 20d18b6f47cb74be76d91568cfc0e0f51a47f1dd /tests/svtypes/static_cast_zero.ys | |
| parent | b1707407a0912fe44ecf83f6f8e64b13a1c4daee (diff) | |
| parent | 429d37ff41b5a058fdd0b70f23a55170a973c369 (diff) | |
| download | yosys-8ce4f8790ecf33f7df19e0fb54a749abe026831d.tar.gz yosys-8ce4f8790ecf33f7df19e0fb54a749abe026831d.tar.bz2 yosys-8ce4f8790ecf33f7df19e0fb54a749abe026831d.zip | |
Merge pull request #2179 from splhack/static-cast
Support SystemVerilog Static Cast
Diffstat (limited to 'tests/svtypes/static_cast_zero.ys')
| -rw-r--r-- | tests/svtypes/static_cast_zero.ys | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/svtypes/static_cast_zero.ys b/tests/svtypes/static_cast_zero.ys new file mode 100644 index 000000000..d8335ca1b --- /dev/null +++ b/tests/svtypes/static_cast_zero.ys @@ -0,0 +1,4 @@ +logger -expect error "Static cast with zero or negative size" 1 +read_verilog -sv <<EOT +module top; wire [7:0] a = 0'(a); endmodule +EOT |