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| author | Jeff Wang <jjj11x@gmail.com> | 2020-02-03 01:12:24 -0500 |
|---|---|---|
| committer | Jeff Wang <jeff.wang@utexas.edu> | 2020-02-17 04:42:42 -0500 |
| commit | d12ba42a741464d410773471813d0a78a7ae1db2 (patch) | |
| tree | 218359053ff4c633932531a279cc8635244b88ec /tests/svtypes/enum_simple.sv | |
| parent | 6320f2692bc97d9d447622c1ba55a90cfe9dd411 (diff) | |
| download | yosys-d12ba42a741464d410773471813d0a78a7ae1db2.tar.gz yosys-d12ba42a741464d410773471813d0a78a7ae1db2.tar.bz2 yosys-d12ba42a741464d410773471813d0a78a7ae1db2.zip | |
add attributes for enumerated values in ilang
- information also useful for strongly-typed enums (not implemented)
- resolves enum values in ilang part of #1594
- still need to output enums to VCD (or better yet FST) files
Diffstat (limited to 'tests/svtypes/enum_simple.sv')
| -rw-r--r-- | tests/svtypes/enum_simple.sv | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/svtypes/enum_simple.sv b/tests/svtypes/enum_simple.sv index 0c3f55c34..ccaf50da0 100644 --- a/tests/svtypes/enum_simple.sv +++ b/tests/svtypes/enum_simple.sv @@ -6,7 +6,7 @@ module enum_simple(input clk, input rst); ts0, ts1, ts2, ts3 } states_t; (states_t) state; - (states_t) enum_const = s1; + (states_t) enum_const = ts1; always @(posedge clk) begin if (rst) begin @@ -41,7 +41,7 @@ module enum_simple(input clk, input rst); assert(state != 2'h3); assert(s0 == '0); assert(ts0 == '0); - assert(enum_const == s1); + assert(enum_const == ts1); end endmodule |