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authorJannis Harder <me@jix.one>2022-05-11 12:55:53 +0200
committerJannis Harder <me@jix.one>2022-05-11 13:05:27 +0200
commitfada77b8cfcb770a25e1f18543ddc428d9138f74 (patch)
treed64653e6ddd0de0f734bc0c414107c4d8724afbf /tests/sva/sva_value_change_sim.sv
parentc862b1dbfbb3a8e1ec90c483a8364550b3fe840c (diff)
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verific: Use new value change logic also for $stable of wide signals.
I missed this in the previous PR.
Diffstat (limited to 'tests/sva/sva_value_change_sim.sv')
-rw-r--r--tests/sva/sva_value_change_sim.sv23
1 files changed, 21 insertions, 2 deletions
diff --git a/tests/sva/sva_value_change_sim.sv b/tests/sva/sva_value_change_sim.sv
index 80ff309cd..92fe30b23 100644
--- a/tests/sva/sva_value_change_sim.sv
+++ b/tests/sva/sva_value_change_sim.sv
@@ -7,6 +7,8 @@ reg [7:0] counter = 0;
reg a = 0;
reg b = 1;
reg c;
+reg [2:0] wide_a = 3'b10x;
+reg [2:0] wide_b = 'x;
wire a_fell; assign a_fell = $fell(a, @(posedge clk));
wire a_rose; assign a_rose = $rose(a, @(posedge clk));
@@ -20,6 +22,9 @@ wire c_fell; assign c_fell = $fell(c, @(posedge clk));
wire c_rose; assign c_rose = $rose(c, @(posedge clk));
wire c_stable; assign c_stable = $stable(c, @(posedge clk));
+wire wide_a_stable; assign wide_a_stable = $stable(wide_a, @(posedge clk));
+wire wide_b_stable; assign wide_b_stable = $stable(wide_b, @(posedge clk));
+
always @(posedge clk) begin
counter <= counter + 1;
@@ -28,13 +33,20 @@ always @(posedge clk) begin
assert property ( $fell(a) && !$rose(a) && !$stable(a));
assert property (!$fell(b) && $rose(b) && !$stable(b));
assert property (!$fell(c) && !$rose(c) && $stable(c));
+ assert property (!$stable(wide_a));
+ assert property ($stable(wide_b));
a <= 1; b <= 1; c <= 1;
end
- 1: begin a <= 0; b <= 1; c <= 'x; end
+ 1: begin
+ a <= 0; b <= 1; c <= 'x;
+ wide_a <= 3'b101; wide_b <= 3'bxx0;
+ end
2: begin
assert property ( $fell(a) && !$rose(a) && !$stable(a));
assert property (!$fell(b) && !$rose(b) && $stable(b));
assert property (!$fell(c) && !$rose(c) && !$stable(c));
+ assert property (!$stable(wide_a));
+ assert property (!$stable(wide_b));
a <= 0; b <= 0; c <= 0;
end
3: begin a <= 0; b <= 1; c <= 'x; end
@@ -42,9 +54,16 @@ always @(posedge clk) begin
assert property (!$fell(a) && !$rose(a) && $stable(a));
assert property (!$fell(b) && $rose(b) && !$stable(b));
assert property (!$fell(c) && !$rose(c) && !$stable(c));
+ assert property ($stable(wide_a));
+ assert property ($stable(wide_b));
a <= 'x; b <= 'x; c <= 'x;
+ wide_a <= 'x; wide_b <= 'x;
+ end
+ 5: begin
+ a <= 0; b <= 1; c <= 'x;
+ wide_a <= 3'b10x; wide_b <= 'x;
+ counter <= 0;
end
- 5: begin a <= 0; b <= 1; c <= 'x; counter <= 0; end
endcase;
end