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| author | Jannis Harder <me@jix.one> | 2023-03-20 12:50:14 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-03-20 12:52:46 +0100 |
| commit | fb1c2be76ba065a3da04f279b11e1ed2e59c75c5 (patch) | |
| tree | f452376b633c339d43d7e2e16cc991465ebeef25 /tests/sva/nested_clk_else.sv | |
| parent | 61da330a38812a0a394131f9f434c736cb2239cf (diff) | |
| download | yosys-fb1c2be76ba065a3da04f279b11e1ed2e59c75c5.tar.gz yosys-fb1c2be76ba065a3da04f279b11e1ed2e59c75c5.tar.bz2 yosys-fb1c2be76ba065a3da04f279b11e1ed2e59c75c5.zip | |
verilog: Support void functions
The difference between void functions and tasks is that always_comb's
implicit sensitivity list behaves as if functions were inlined, but
ignores signals read only in tasks. This only matters for event based
simulation, and for synthesis we can treat a void function like a task.
Diffstat (limited to 'tests/sva/nested_clk_else.sv')
0 files changed, 0 insertions, 0 deletions