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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-22 16:35:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-22 16:35:46 +0200 |
| commit | 84f15260b5f3d328c75ee385d2fdc2861b4e8f59 (patch) | |
| tree | 87917cc11e9d0d69751ffaed5836ed970d532e26 /tests/sva/basic05.sv | |
| parent | 5be535517cfe9ce4c664e95eb02684305fc268e3 (diff) | |
| download | yosys-84f15260b5f3d328c75ee385d2fdc2861b4e8f59.tar.gz yosys-84f15260b5f3d328c75ee385d2fdc2861b4e8f59.tar.bz2 yosys-84f15260b5f3d328c75ee385d2fdc2861b4e8f59.zip | |
Add more SVA test cases for future Verific work
Diffstat (limited to 'tests/sva/basic05.sv')
| -rw-r--r-- | tests/sva/basic05.sv | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/sva/basic05.sv b/tests/sva/basic05.sv new file mode 100644 index 000000000..03854aaac --- /dev/null +++ b/tests/sva/basic05.sv @@ -0,0 +1,15 @@ +module top (input logic clock, ctrl); + logic read, write, ready; + + demo uut ( + .clock(clock), + .ctrl(ctrl) + ); + + assign read = uut.read; + assign write = uut.write; + assign ready = uut.ready; + + a_rw: assert property ( @(posedge clock) !(read && write) ); + a_wr: assert property ( @(posedge clock) write |-> ready ); +endmodule |