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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-27 11:42:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-27 11:42:05 +0200 |
| commit | b24f73775983eb7a30d50f608ccc8702e54c57c3 (patch) | |
| tree | 1ac774a5810f821740f6c721e348a34b8c9408ac /tests/sva/basic00.sv | |
| parent | 90d8329f642e710e8d4ce358cfb9543b85bcd822 (diff) | |
| download | yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.tar.gz yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.tar.bz2 yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.zip | |
Improve SVA tests, add Makefile and scripts
Diffstat (limited to 'tests/sva/basic00.sv')
| -rw-r--r-- | tests/sva/basic00.sv | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/sva/basic00.sv b/tests/sva/basic00.sv index 387f3deef..30c37f5f1 100644 --- a/tests/sva/basic00.sv +++ b/tests/sva/basic00.sv @@ -2,6 +2,11 @@ module top (input clk, reset, antecedent, output reg consequent); always @(posedge clk) consequent <= reset ? 0 : antecedent; +`ifdef FAIL test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |-> consequent ) else $error("Failed with consequent = ", $sampled(consequent)); +`else + test_assert: assert property ( @(posedge clk) disable iff (reset) antecedent |=> consequent ) + else $error("Failed with consequent = ", $sampled(consequent)); +`endif endmodule |