diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 12:37:57 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 12:37:57 -0800 |
| commit | c761fa49b73e9ad3680b05e89442adb6fb22b543 (patch) | |
| tree | f8b62efedc50d2f0a08cd3c4c2d29c198d87d0f7 /tests/simple_abc9 | |
| parent | 0ab1e496dc601f8e9d5efbcc5b2be7cf6b2d9673 (diff) | |
| download | yosys-c761fa49b73e9ad3680b05e89442adb6fb22b543.tar.gz yosys-c761fa49b73e9ad3680b05e89442adb6fb22b543.tar.bz2 yosys-c761fa49b73e9ad3680b05e89442adb6fb22b543.zip | |
Missing endmodule
Diffstat (limited to 'tests/simple_abc9')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 596a52501..6bdd3bc32 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -288,3 +288,4 @@ endmodule module abc9_test033(input clk, d, output reg q1, q2); always @(posedge clk) q1 <= d; always @(posedge clk) q2 <= q1; +endmodule |