diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:13:28 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-21 16:13:28 -0800 |
| commit | 911a152b39959137b26e68581a6cacbcabb4ab1d (patch) | |
| tree | 8b066629d71598b65532b27623634e53e41b69a9 /tests/simple_abc9 | |
| parent | a5767474830756319ce0fff53b81573701ec0cd2 (diff) | |
| download | yosys-911a152b39959137b26e68581a6cacbcabb4ab1d.tar.gz yosys-911a152b39959137b26e68581a6cacbcabb4ab1d.tar.bz2 yosys-911a152b39959137b26e68581a6cacbcabb4ab1d.zip | |
Add test
Diffstat (limited to 'tests/simple_abc9')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 1844bac20..13c505eec 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -268,7 +268,12 @@ assign o = { 1'b1, 1'bx }; assign p = { 1'b1, 1'bx, 1'b0 }; endmodule -module abc9_test029(input clk1, clk2, input d, output reg q1, q2); +module abc9_test029(input clk1, clk2, d, output reg q1, q2); always @(posedge clk1) q1 <= d; always @(negedge clk2) q2 <= q1; endmodule + +module abc9_test030(input clk, d, output reg q1, q2); +always @(posedge clk) q1 <= d; +always @(posedge clk) q2 <= q1; +endmodule |