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| author | whitequark <whitequark@whitequark.org> | 2020-01-01 08:27:47 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-02-06 16:52:51 +0000 |
| commit | 081d9318bcf1ee13549ddcb0983cba5f00b4272c (patch) | |
| tree | 9cc64505a7e60cfec38ef80b93d3b6721a50919d /tests/simple_abc9 | |
| parent | 3f4460a1869ccfd6225379d18ade195f165841a4 (diff) | |
| download | yosys-081d9318bcf1ee13549ddcb0983cba5f00b4272c.tar.gz yosys-081d9318bcf1ee13549ddcb0983cba5f00b4272c.tar.bz2 yosys-081d9318bcf1ee13549ddcb0983cba5f00b4272c.zip | |
ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
This commit tries to carefully follow the documented behavior of LSE
and Synplify. It will use `syn_ramstyle` attribute if there are any
write ports, and `syn_romstyle` attribute otherwise.
* LSE supports both `syn_ramstyle` and `syn_romstyle`.
* Synplify only supports `syn_ramstyle`, with same values as LSE.
* Synplify also supports `syn_rw_conflict_logic`, which is not
documented as supported for LSE.
Limitations of the Yosys implementation:
* LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"`
syntax to turn off insertion of transparency logic. There is
currently no way to support multiple valued attributes in
memory_bram. It is also not clear if that is a good idea, since
it can cause sim/synth mismatches.
* LSE/Synplify/1364.1 support block ROM inference from full case
statements. Yosys does not currently perform this transformation.
* LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes
from the module to the inner memories. There is currently no way
to do this in Yosys (attrmvcp only works on cells and wires).
Diffstat (limited to 'tests/simple_abc9')
0 files changed, 0 insertions, 0 deletions