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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-07 11:53:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-07 11:53:46 +0200 |
| commit | 169de05f3be779dd936ed5e0efea6a6055d5b187 (patch) | |
| tree | 435adec6e283570417ed09ad50a02480ecd72536 /tests/simple | |
| parent | 7116621d221d5c35e7ca8c5f0fa79771ae3a4173 (diff) | |
| parent | a0b57f2a6ffae3b5770e38bf5a9af0df50db8522 (diff) | |
| download | yosys-169de05f3be779dd936ed5e0efea6a6055d5b187.tar.gz yosys-169de05f3be779dd936ed5e0efea6a6055d5b187.tar.bz2 yosys-169de05f3be779dd936ed5e0efea6a6055d5b187.zip | |
Merge branch 'tux3-implicit_named_connection'
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/implicit_ports.sv | 16 | ||||
| -rwxr-xr-x | tests/simple/run-test.sh | 3 |
2 files changed, 18 insertions, 1 deletions
diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv new file mode 100644 index 000000000..8b0a6f386 --- /dev/null +++ b/tests/simple/implicit_ports.sv @@ -0,0 +1,16 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); + wire cin = 1; + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh index aaa1cf940..967ac49f2 100755 --- a/tests/simple/run-test.sh +++ b/tests/simple/run-test.sh @@ -17,4 +17,5 @@ if ! which iverilog > /dev/null ; then exit 1 fi -exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v +shopt -s nullglob +exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.{sv,v} |