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| author | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-01 13:16:01 -0700 |
|---|---|---|
| committer | Jim Lawson <ucbjrl@berkeley.edu> | 2019-05-01 13:16:01 -0700 |
| commit | 38f5424f92389d6f4fdf020b214023b2b6efa71a (patch) | |
| tree | 0c3bb206b6ec82177eba5794e37d9b422af1a351 /tests/simple/xfirrtl | |
| parent | e35fe1344dd4c8f11632ed2a7f5b0463352a1ee4 (diff) | |
| download | yosys-38f5424f92389d6f4fdf020b214023b2b6efa71a.tar.gz yosys-38f5424f92389d6f4fdf020b214023b2b6efa71a.tar.bz2 yosys-38f5424f92389d6f4fdf020b214023b2b6efa71a.zip | |
Fix #938 - Crash occurs in case when use write_firrtl command
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).
Diffstat (limited to 'tests/simple/xfirrtl')
| -rw-r--r-- | tests/simple/xfirrtl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 50d693513..ba61a4476 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -16,6 +16,7 @@ operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules +retime.v Initial value (11110101) for (retime_test.ff) not supported scopes.v original verilog issues ( -x where x isn't declared signed) sincos.v $adff specify.v no code (empty module generates error |