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| author | Jannis Harder <me@jix.one> | 2022-05-11 12:55:53 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-05-11 13:05:27 +0200 |
| commit | fada77b8cfcb770a25e1f18543ddc428d9138f74 (patch) | |
| tree | d64653e6ddd0de0f734bc0c414107c4d8724afbf /tests/simple/verilog_primitives.v | |
| parent | c862b1dbfbb3a8e1ec90c483a8364550b3fe840c (diff) | |
| download | yosys-fada77b8cfcb770a25e1f18543ddc428d9138f74.tar.gz yosys-fada77b8cfcb770a25e1f18543ddc428d9138f74.tar.bz2 yosys-fada77b8cfcb770a25e1f18543ddc428d9138f74.zip | |
verific: Use new value change logic also for $stable of wide signals.
I missed this in the previous PR.
Diffstat (limited to 'tests/simple/verilog_primitives.v')
0 files changed, 0 insertions, 0 deletions