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| author | Zachary Snow <zach@zachjs.com> | 2021-03-25 14:06:05 -0400 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-05-25 16:16:46 -0400 |
| commit | 0795b3ec076d8d2c0aa0d954b707271bd2f064bf (patch) | |
| tree | 5b6c7eaef762a9dc76bb0507c76d0addcbdbb736 /tests/simple/specify.v | |
| parent | 15f35d6754af619accdf63030e0a5ad3085cec16 (diff) | |
| download | yosys-0795b3ec076d8d2c0aa0d954b707271bd2f064bf.tar.gz yosys-0795b3ec076d8d2c0aa0d954b707271bd2f064bf.tar.bz2 yosys-0795b3ec076d8d2c0aa0d954b707271bd2f064bf.zip | |
verilog: fix case expression sign and width handling
- The case expression and case item expressions are extended to the
maximum width among them, and are only interpreted as signed if all of
them are signed
- Add overall width and sign detection for AST_CASE
- Add sign argument to genWidthRTLIL helper
- Coverage for both const and non-const case statements
Diffstat (limited to 'tests/simple/specify.v')
0 files changed, 0 insertions, 0 deletions