diff options
author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 13:01:45 +0200 |
---|---|---|
committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 13:01:45 +0200 |
commit | 50f22ff30c921c90f686879455117c7c2c9f96d5 (patch) | |
tree | 9ee57923c22af5d0559288452ca0c02f0747f2be /tests/simple/memory.v | |
parent | 0520bfea892291a131134411d587034fcd36bf1c (diff) | |
download | yosys-50f22ff30c921c90f686879455117c7c2c9f96d5.tar.gz yosys-50f22ff30c921c90f686879455117c7c2c9f96d5.tar.bz2 yosys-50f22ff30c921c90f686879455117c7c2c9f96d5.zip |
Renamed some of the test cases in tests/simple to avoid name collisions
Diffstat (limited to 'tests/simple/memory.v')
-rw-r--r-- | tests/simple/memory.v | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v index ae63e8a16..9fed1bf3b 100644 --- a/tests/simple/memory.v +++ b/tests/simple/memory.v @@ -1,5 +1,5 @@ -module test00(clk, setA, setB, y); +module memtest00(clk, setA, setB, y); input clk, setA, setB; output y; @@ -16,7 +16,7 @@ endmodule // ---------------------------------------------------------- -module test01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value); +module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value); input clk, wr_en; input [3:0] wr_addr, rd_addr; @@ -36,7 +36,7 @@ endmodule // ---------------------------------------------------------- -module test02(clk, setA, setB, addr, bit, y1, y2, y3, y4); +module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4); input clk, setA, setB; input [1:0] addr; @@ -77,7 +77,7 @@ endmodule // ---------------------------------------------------------- -module test03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); +module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); input clk, wr_enable; input [3:0] wr_addr, wr_data, rd_addr; @@ -95,7 +95,7 @@ endmodule // ---------------------------------------------------------- -module test04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); +module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data); input clk, wr_enable; input [3:0] wr_addr, wr_data, rd_addr; @@ -116,7 +116,7 @@ endmodule // ---------------------------------------------------------- -module test05(clk, addr, wdata, rdata, wen); +module memtest05(clk, addr, wdata, rdata, wen); input clk; input [1:0] addr; @@ -137,7 +137,7 @@ endmodule // ---------------------------------------------------------- -module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); +module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); (* gentb_constant=0 *) wire rst; reg [7:0] test [0:7]; integer i; @@ -156,7 +156,7 @@ module test06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, outpu assign dout = test[idx]; endmodule -module test06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); +module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout); (* gentb_constant=0 *) wire rst; reg [7:0] test [0:7]; integer i; @@ -177,7 +177,7 @@ endmodule // ---------------------------------------------------------- -module test07(clk, addr, woffset, wdata, rdata); +module memtest07(clk, addr, woffset, wdata, rdata); input clk; input [1:0] addr; |