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author | Clifford Wolf <clifford@clifford.at> | 2013-03-24 15:25:08 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-03-24 15:25:08 +0100 |
commit | d9bc024d29dd780e34eb6c9c3e84feab763eeb10 (patch) | |
tree | 5089202d198ffb0402219e697f820c5d70c1b5ba /tests/simple/mem_arst.v | |
parent | e1a80b356e3af1ecd1cdb796ecb0ce2773dbd003 (diff) | |
download | yosys-d9bc024d29dd780e34eb6c9c3e84feab763eeb10.tar.gz yosys-d9bc024d29dd780e34eb6c9c3e84feab763eeb10.tar.bz2 yosys-d9bc024d29dd780e34eb6c9c3e84feab763eeb10.zip |
Renamed hansimem.v test case to mem_arst.v
Diffstat (limited to 'tests/simple/mem_arst.v')
-rw-r--r-- | tests/simple/mem_arst.v | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v new file mode 100644 index 000000000..4022f57cd --- /dev/null +++ b/tests/simple/mem_arst.v @@ -0,0 +1,43 @@ + +module MyMem #( + parameter AddrWidth = 4, + parameter DataWidth = 4) ( + (* gentb_constant = 1 *) + input Reset_n_i, + input Clk_i, + input [AddrWidth-1:0] Addr_i, + input [DataWidth-1:0] Data_i, + output [DataWidth-1:0] Data_o, + input WR_i); + + reg Data_o; + + localparam Size = 2**AddrWidth; + + (* mem2reg *) + reg [DataWidth-1:0] Mem[Size-1:0]; + + integer i; + + always @(negedge Reset_n_i or posedge Clk_i) + begin + if (!Reset_n_i) + begin + Data_o <= 'bx; + for (i=0; i<Size; i=i+1) + begin + Mem[i] <= 0; + end + end + else + begin + Data_o <= Mem[Addr_i]; + if (WR_i) + begin + Mem[Addr_i] <= Data_i; + end + end + end + +endmodule + |