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| author | whitequark <whitequark@whitequark.org> | 2018-12-07 18:48:06 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-07 18:55:08 +0000 |
| commit | 7fe770a441a129c509fd4da04b60ada942a28bc8 (patch) | |
| tree | 03cb149cb5da3a9638b5919019db38ee6b754db7 /tests/simple/mem_arst.v | |
| parent | 435776120a40ed06ea42ca63bcca231913507ac3 (diff) | |
| download | yosys-7fe770a441a129c509fd4da04b60ada942a28bc8.tar.gz yosys-7fe770a441a129c509fd4da04b60ada942a28bc8.tar.bz2 yosys-7fe770a441a129c509fd4da04b60ada942a28bc8.zip | |
write_verilog: correctly map RTLIL `sync init`.
Diffstat (limited to 'tests/simple/mem_arst.v')
0 files changed, 0 insertions, 0 deletions