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| author | Claire Wolf <claire@symbioticeda.com> | 2020-03-08 16:12:12 +0100 |
|---|---|---|
| committer | Claire Wolf <claire@symbioticeda.com> | 2020-03-08 16:12:12 +0100 |
| commit | a7cc4673c3f75f414a82c81a507da5042bba361f (patch) | |
| tree | 616a31593f4be7283072a1e0da6b4187af6f7c04 /tests/simple/implicit_ports.v | |
| parent | bfeba9ad11847e6a0cbe47f880f3642d5e3a8061 (diff) | |
| download | yosys-a7cc4673c3f75f414a82c81a507da5042bba361f.tar.gz yosys-a7cc4673c3f75f414a82c81a507da5042bba361f.tar.bz2 yosys-a7cc4673c3f75f414a82c81a507da5042bba361f.zip | |
Fix partsel expr bit width handling and add test case
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Diffstat (limited to 'tests/simple/implicit_ports.v')
0 files changed, 0 insertions, 0 deletions