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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-25 13:01:45 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-25 13:01:45 +0200 |
| commit | 50f22ff30c921c90f686879455117c7c2c9f96d5 (patch) | |
| tree | 9ee57923c22af5d0559288452ca0c02f0747f2be /tests/simple/generate.v | |
| parent | 0520bfea892291a131134411d587034fcd36bf1c (diff) | |
| download | yosys-50f22ff30c921c90f686879455117c7c2c9f96d5.tar.gz yosys-50f22ff30c921c90f686879455117c7c2c9f96d5.tar.bz2 yosys-50f22ff30c921c90f686879455117c7c2c9f96d5.zip | |
Renamed some of the test cases in tests/simple to avoid name collisions
Diffstat (limited to 'tests/simple/generate.v')
| -rw-r--r-- | tests/simple/generate.v | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 39e573a73..24eb4462c 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -1,5 +1,5 @@ -module test1(clk, a, b, y); +module gen_test1(clk, a, b, y); input clk; input [7:0] a, b; @@ -40,7 +40,7 @@ endmodule // ------------------------------------------ -module test2(clk, a, b, y); +module gen_test2(clk, a, b, y); input clk; input [7:0] a, b; @@ -67,7 +67,7 @@ endmodule // ------------------------------------------ -module test3(a, b, sel, y, z); +module gen_test3(a, b, sel, y, z); input [3:0] a, b; input sel; |