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| author | Jannis Harder <me@jix.one> | 2023-03-20 16:10:19 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-03-20 16:10:19 +0100 |
| commit | dc0a799c06a48a1d9612743ed0b70458309462f0 (patch) | |
| tree | f452376b633c339d43d7e2e16cc991465ebeef25 /tests/simple/fsm.v | |
| parent | 61da330a38812a0a394131f9f434c736cb2239cf (diff) | |
| parent | fb1c2be76ba065a3da04f279b11e1ed2e59c75c5 (diff) | |
| download | yosys-dc0a799c06a48a1d9612743ed0b70458309462f0.tar.gz yosys-dc0a799c06a48a1d9612743ed0b70458309462f0.tar.bz2 yosys-dc0a799c06a48a1d9612743ed0b70458309462f0.zip | |
Merge pull request #3708 from jix/void_func
verilog: Support void functions
Diffstat (limited to 'tests/simple/fsm.v')
0 files changed, 0 insertions, 0 deletions