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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:00:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-20 19:00:36 -0700 |
| commit | e612dade12b30bdee15b7dd2535af51e5ec1614d (patch) | |
| tree | e38be54476c557471cc8a30bc8c140d7c2797b3a /tests/simple/defvalue.sv | |
| parent | 014606affe3f1753ac16d2afd684967d72d83746 (diff) | |
| parent | 477e566e8d203ec7754c90fc845d7f3f759f2974 (diff) | |
| download | yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.tar.gz yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.tar.bz2 yosys-e612dade12b30bdee15b7dd2535af51e5ec1614d.zip | |
Merge remote-tracking branch 'origin/master' into xaig
Diffstat (limited to 'tests/simple/defvalue.sv')
| -rw-r--r-- | tests/simple/defvalue.sv | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv new file mode 100644 index 000000000..b0a087ecb --- /dev/null +++ b/tests/simple/defvalue.sv @@ -0,0 +1,22 @@ +module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2); + cnt #(1) foo (.clock, .cnt(cnt1), .delta); + cnt #(2) bar (.clock, .cnt(cnt2)); +endmodule + +module cnt #( + parameter integer initval = 0 +) ( + input clock, + output logic [3:0] cnt = initval, +`ifdef __ICARUS__ + input [3:0] delta +`else + input [3:0] delta = 10 +`endif +); +`ifdef __ICARUS__ + assign (weak0, weak1) delta = 10; +`endif + always @(posedge clock) + cnt <= cnt + delta; +endmodule |