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| author | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:17:56 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2013-03-31 11:17:56 +0200 |
| commit | 5640b7d6078a681e33e85f06920394204f41c875 (patch) | |
| tree | 96ebae5ed0626ae5238fe8b794e50e0cb9d87e7c /tests/simple/always03.v | |
| parent | 04843bdcbeb62a202a6372ea5464de8c7ea66820 (diff) | |
| download | yosys-5640b7d6078a681e33e85f06920394204f41c875.tar.gz yosys-5640b7d6078a681e33e85f06920394204f41c875.tar.bz2 yosys-5640b7d6078a681e33e85f06920394204f41c875.zip | |
Added test cases from 2012 paper on comparison of foss verilog synthesis tools
Diffstat (limited to 'tests/simple/always03.v')
| -rw-r--r-- | tests/simple/always03.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/simple/always03.v b/tests/simple/always03.v new file mode 100644 index 000000000..5542175e5 --- /dev/null +++ b/tests/simple/always03.v @@ -0,0 +1,22 @@ +module uut_always03(clock, in1, in2, in3, in4, in5, in6, in7, out1, out2, out3); + +input clock, in1, in2, in3, in4, in5, in6, in7; +output out1, out2, out3; +reg out1, out2, out3; + +always @(posedge clock) begin + out1 = in1; + if (in2) + out1 = !out1; + out2 <= out1; + if (in3) + out2 <= out2; + if (in4) + if (in5) + out3 <= in6; + else + out3 <= in7; + out1 = out1 ^ out2; +end + +endmodule |