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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-15 09:35:53 +0100 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:27:59 +0100 |
commit | 271ac28b417be00d7be1cc898762c8e425a0aae3 (patch) | |
tree | fcff14974c070b2615e8eda981e5b811fc4e8905 /tests/sim/tb/tb_sdff.v | |
parent | fb22d7cdc411ec52672cb7f13364651c564872db (diff) | |
download | yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.tar.gz yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.tar.bz2 yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.zip |
Added test cases
Diffstat (limited to 'tests/sim/tb/tb_sdff.v')
-rwxr-xr-x | tests/sim/tb/tb_sdff.v | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/tests/sim/tb/tb_sdff.v b/tests/sim/tb/tb_sdff.v new file mode 100755 index 000000000..f8e2a1c9d --- /dev/null +++ b/tests/sim/tb/tb_sdff.v @@ -0,0 +1,48 @@ +`timescale 1ns/1ns +module tb_sdff(); + reg clk = 0; + reg rst = 0; + reg d = 0; + wire q; + + sdff uut(.clk(clk),.d(d),.rst(rst),.q(q)); + + always + #(5) clk <= !clk; + + initial + begin + $dumpfile("tb_sdff"); + $dumpvars(0,tb_sdff); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + rst = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule |