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author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:58:51 +0100 |
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committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:58:51 +0100 |
commit | 21baf48e04bfb75527a6c04f1e98b34e62b8eec4 (patch) | |
tree | 59010c1cb5c351fc253a40217102d025865b2d79 /tests/sim/tb/tb_dlatchsr.v | |
parent | 271ac28b417be00d7be1cc898762c8e425a0aae3 (diff) | |
download | yosys-21baf48e04bfb75527a6c04f1e98b34e62b8eec4.tar.gz yosys-21baf48e04bfb75527a6c04f1e98b34e62b8eec4.tar.bz2 yosys-21baf48e04bfb75527a6c04f1e98b34e62b8eec4.zip |
test dlatchsr and adlatch
Diffstat (limited to 'tests/sim/tb/tb_dlatchsr.v')
-rwxr-xr-x | tests/sim/tb/tb_dlatchsr.v | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/tests/sim/tb/tb_dlatchsr.v b/tests/sim/tb/tb_dlatchsr.v new file mode 100755 index 000000000..0105d3288 --- /dev/null +++ b/tests/sim/tb/tb_dlatchsr.v @@ -0,0 +1,65 @@ +`timescale 1ns/1ns +module tb_dlatchsr(); + reg d = 0; + reg set = 0; + reg clr = 0; + wire q; + + dlatchsr uut(.d(d),.set(set),.clr(clr),.q(q)); + + initial + begin + $dumpfile("tb_dlatchsr"); + $dumpvars(0,tb_dlatchsr); + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + clr = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + clr = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + set = 1; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + set = 0; + #10 + d = 1; + #10 + d = 0; + #10 + d = 1; + #10 + d = 0; + #10 + $finish; + end +endmodule |