diff options
| author | Miodrag Milanović <mmicko@gmail.com> | 2022-02-21 17:57:44 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-21 17:57:44 +0100 |
| commit | d0b72e75d95828743b38184ee977c3c56f259b38 (patch) | |
| tree | d4cdb702831ad471a26c4f96f70900f701166a05 /tests/sim/sim_adlatch.ys | |
| parent | d0f4d0b153572ddee5f19831f40b9c40eb480db0 (diff) | |
| parent | fd3f08753a2c577bb87ad332329213c58d4a9326 (diff) | |
| download | yosys-d0b72e75d95828743b38184ee977c3c56f259b38.tar.gz yosys-d0b72e75d95828743b38184ee977c3c56f259b38.tar.bz2 yosys-d0b72e75d95828743b38184ee977c3c56f259b38.zip | |
Merge pull request #3203 from YosysHQ/micko/sim_ff
Simulation for various FF types
Diffstat (limited to 'tests/sim/sim_adlatch.ys')
| -rw-r--r-- | tests/sim/sim_adlatch.ys | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/tests/sim/sim_adlatch.ys b/tests/sim/sim_adlatch.ys new file mode 100644 index 000000000..eece7dc0d --- /dev/null +++ b/tests/sim/sim_adlatch.ys @@ -0,0 +1,10 @@ +read_verilog -icells <<EOT +module adlatch(input d, rst, en, output reg q); +$adlatch #(.EN_POLARITY(1'b1), .ARST_POLARITY(1'b1), .ARST_VALUE(1'b0), .WIDTH(1)) uut (.EN(en), .ARST(rst), .D(d), .Q(q)); +endmodule +EOT +proc +opt_dff +stat +select -assert-count 1 t:$adlatch +sim -r tb_adlatch.fst -scope tb_adlatch.uut -sim-cmp adlatch |