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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:58:51 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:58:51 +0100 |
| commit | 21baf48e04bfb75527a6c04f1e98b34e62b8eec4 (patch) | |
| tree | 59010c1cb5c351fc253a40217102d025865b2d79 /tests/sim/dlatchsr.v | |
| parent | 271ac28b417be00d7be1cc898762c8e425a0aae3 (diff) | |
| download | yosys-21baf48e04bfb75527a6c04f1e98b34e62b8eec4.tar.gz yosys-21baf48e04bfb75527a6c04f1e98b34e62b8eec4.tar.bz2 yosys-21baf48e04bfb75527a6c04f1e98b34e62b8eec4.zip | |
test dlatchsr and adlatch
Diffstat (limited to 'tests/sim/dlatchsr.v')
| -rw-r--r-- | tests/sim/dlatchsr.v | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/sim/dlatchsr.v b/tests/sim/dlatchsr.v new file mode 100644 index 000000000..1d13ac2ad --- /dev/null +++ b/tests/sim/dlatchsr.v @@ -0,0 +1,11 @@ +module dlatchsr( input d, set, clr, en, output reg q ); + always @* begin + if ( clr ) + q = 0; + else if (set) + q = 1; + else + if (en) + q = d; + end +endmodule |