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| author | Clifford Wolf <clifford@clifford.at> | 2014-07-20 18:54:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-07-20 18:54:06 +0200 |
| commit | e9506bb2da9640cebc325e33a678d352d36a909e (patch) | |
| tree | 73975b4e60d5615d92eca10b59941de4beebb702 /tests/share | |
| parent | 7a6d578b81581f5217b717dcd601cfba2d4a4d0f (diff) | |
| download | yosys-e9506bb2da9640cebc325e33a678d352d36a909e.tar.gz yosys-e9506bb2da9640cebc325e33a678d352d36a909e.tar.bz2 yosys-e9506bb2da9640cebc325e33a678d352d36a909e.zip | |
Supercell creation for $div/$mod worked all along, fixed test benches
Diffstat (limited to 'tests/share')
| -rw-r--r-- | tests/share/generate.py | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/share/generate.py b/tests/share/generate.py index fa17080f9..9e5bef7ae 100644 --- a/tests/share/generate.py +++ b/tests/share/generate.py @@ -46,5 +46,5 @@ for idx in range(100): print('rename uut_%05d gate' % idx) print('share -aggressive gate') print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter') - print('sat -verify -prove trigger 0 -show-inputs -show-outputs miter') + print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter') |