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| author | Clifford Wolf <clifford@clifford.at> | 2018-05-17 14:03:58 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-05-17 14:03:58 +0200 |
| commit | c3be94e967c904d4b7a0591fdaa2d86bc926ec41 (patch) | |
| tree | a2bf6419d36745d2d30c45f7a60060ccc57b49b9 /tests/sat | |
| parent | a7281930c5877b34e072d90d5ca013f8fda7e2cc (diff) | |
| parent | faac2c559565a25e58ce95a7ea873df0c30375dc (diff) | |
| download | yosys-c3be94e967c904d4b7a0591fdaa2d86bc926ec41.tar.gz yosys-c3be94e967c904d4b7a0591fdaa2d86bc926ec41.tar.bz2 yosys-c3be94e967c904d4b7a0591fdaa2d86bc926ec41.zip | |
Merge pull request #551 from olofk/ice40_cells_sim_ports
Avoid mixing module port declaration styles in ice40 cells_sim.v
Diffstat (limited to 'tests/sat')
0 files changed, 0 insertions, 0 deletions