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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-04 10:01:06 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-04 10:01:06 +0100 |
| commit | 6db23de7b13c57eb82489d4bf2f0658b6deb4488 (patch) | |
| tree | 4e1affec5076888ef58109d4eaaa508d3d2d8005 /tests/sat | |
| parent | 7ef6da4c7d418b53ea2868ea452a856cfb2d5b21 (diff) | |
| download | yosys-6db23de7b13c57eb82489d4bf2f0658b6deb4488.tar.gz yosys-6db23de7b13c57eb82489d4bf2f0658b6deb4488.tar.bz2 yosys-6db23de7b13c57eb82489d4bf2f0658b6deb4488.zip | |
bug fix and cleanups
Diffstat (limited to 'tests/sat')
| -rw-r--r-- | tests/sat/grom.ys | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/sat/grom.ys b/tests/sat/grom.ys index 2c2cd71da..da0f3b620 100644 --- a/tests/sat/grom.ys +++ b/tests/sat/grom.ys @@ -1,9 +1,9 @@ read_verilog grom_computer.v grom_cpu.v alu.v ram_memory.v; prep -top grom_computer; -sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -a -n 80 +sim -clock clk -reset reset -fst grom.fst -vcd grom.vcd -n 80 sim -clock clk -r grom.fst -scope grom_computer -start 25ns -stop 100ns -sim-cmp sim -clock clk -r grom.fst -scope grom_computer -stop 100ns -sim-gold -sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate -a +sim -clock clk -r grom.fst -scope grom_computer -n 10 -sim-gate |