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author | Clifford Wolf <clifford@clifford.at> | 2014-02-07 20:26:40 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-02-07 20:30:56 +0100 |
commit | 244e8ce1f42bce47b3426e6679ed0ba5dadd8da6 (patch) | |
tree | b374e5f99803bc2e991c965e4ac3b69280c265b6 /tests/sat/splice.ys | |
parent | 08aa1062b4fbaa507091b9015811104d93da3315 (diff) | |
download | yosys-244e8ce1f42bce47b3426e6679ed0ba5dadd8da6.tar.gz yosys-244e8ce1f42bce47b3426e6679ed0ba5dadd8da6.tar.bz2 yosys-244e8ce1f42bce47b3426e6679ed0ba5dadd8da6.zip |
Added splice command
Diffstat (limited to 'tests/sat/splice.ys')
-rw-r--r-- | tests/sat/splice.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/sat/splice.ys b/tests/sat/splice.ys new file mode 100644 index 000000000..365a4e2fd --- /dev/null +++ b/tests/sat/splice.ys @@ -0,0 +1,14 @@ +read_verilog splice.v +hierarchy -check; opt +copy test gold + +cd test +splice +# show + +cd .. +rename test gate +miter -equiv -make_assert -make_outputs gold gate miter + +flatten miter +sat -verify -prove-asserts -show-inputs -show-outputs miter |