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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-01 02:14:19 -0800 |
| commit | 136842b1ef18b850b518705ff3e6df3958f28e0c (patch) | |
| tree | abcdddaf53bafd5e34e9aa278ffbe3d001b60cc4 /tests/sat/initval.ys | |
| parent | 705e520a527864dc32f1934bb4b2b94d75f8f0ec (diff) | |
| parent | a1c840ca5d6e8b580e21ae48550570aa9665741a (diff) | |
| download | yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.gz yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.tar.bz2 yosys-136842b1ef18b850b518705ff3e6df3958f28e0c.zip | |
Merge branch 'master' into eddie/submod_po
Diffstat (limited to 'tests/sat/initval.ys')
| -rw-r--r-- | tests/sat/initval.ys | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 2079d2f34..1436724b0 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,3 +2,14 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts + +design -reset +read_verilog -icells <<EOT +module top(input clk, i, output [1:0] o); +(* init = 2'bx0 *) +wire [1:0] o; +assign o[1] = o[0]; +$_DFF_P_ dff (.C(clk), .D(i), .Q(o[0])); +endmodule +EOT +sat -seq 1 |