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author | Clifford Wolf <clifford@clifford.at> | 2014-07-05 11:17:40 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-05 11:18:38 +0200 |
commit | 3b52121d328d45a5d4269fd0e8de9af948c0216e (patch) | |
tree | 59d61572353b98e449d72f4802c4e7c164f7b5eb /tests/sat/initval.v | |
parent | ee8ad72fd950e1ee204e5c97155a50b8b1445dec (diff) | |
download | yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.tar.gz yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.tar.bz2 yosys-3b52121d328d45a5d4269fd0e8de9af948c0216e.zip |
now ignore init attributes on non-register wires in sat command
Diffstat (limited to 'tests/sat/initval.v')
-rw-r--r-- | tests/sat/initval.v | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v new file mode 100644 index 000000000..5b661f8d6 --- /dev/null +++ b/tests/sat/initval.v @@ -0,0 +1,15 @@ +module test(input clk, input [3:0] bar, output [3:0] foo); + reg [3:0] foo = 0; + reg [3:0] last_bar = 0; + + always @* + foo[1:0] <= bar[1:0]; + + always @(posedge clk) + foo[3:2] <= bar[3:2]; + + always @(posedge clk) + last_bar <= bar; + + assert property (foo == {last_bar[3:2], bar[1:0]}); +endmodule |