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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-12 23:36:28 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-13 00:37:14 +0200 |
| commit | 990c9b8e11446a306ea577ab8154e0cad155c4d1 (patch) | |
| tree | 5fb931d5e759222dddb392dfa53b73d70e763db6 /tests/proc | |
| parent | c862b1dbfbb3a8e1ec90c483a8364550b3fe840c (diff) | |
| download | yosys-990c9b8e11446a306ea577ab8154e0cad155c4d1.tar.gz yosys-990c9b8e11446a306ea577ab8154e0cad155c4d1.tar.bz2 yosys-990c9b8e11446a306ea577ab8154e0cad155c4d1.zip | |
Add proc_rom pass.
Diffstat (limited to 'tests/proc')
| -rw-r--r-- | tests/proc/proc_rom.ys | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/tests/proc/proc_rom.ys b/tests/proc/proc_rom.ys new file mode 100644 index 000000000..c854e732f --- /dev/null +++ b/tests/proc/proc_rom.ys @@ -0,0 +1,43 @@ +read_verilog << EOT + +module top(input [3:0] a, input en, output [7:0] d); + +always @* + if (en) + case(a) + 4'h0: d <= 8'h12; + 4'h1: d <= 8'h34; + 4'h2: d <= 8'h56; + 4'h3: d <= 8'h78; + 4'h4: d <= 8'h9a; + 4'h5: d <= 8'hbc; + 4'h6: d <= 8'hde; + 4'h7: d <= 8'hff; + 4'h8: d <= 8'h61; + 4'h9: d <= 8'h49; + 4'ha: d <= 8'h36; + 4'hb: d <= 8'h81; + 4'hc: d <= 8'h8c; + 4'hd: d <= 8'ha9; + 4'he: d <= 8'h99; + 4'hf: d <= 8'h51; + endcase + else + d <= 0; + +endmodule + +EOT + +hierarchy -auto-top + +design -save orig +proc +memory +opt_dff +design -stash postopt +design -load orig +proc -norom +design -stash preopt + +equiv_opt -assert -run prepare: dummy |