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author | whitequark <whitequark@whitequark.org> | 2019-08-19 16:44:23 +0000 |
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committer | whitequark <whitequark@whitequark.org> | 2019-08-19 16:44:23 +0000 |
commit | 4a942ba7b9bb76f207adf23369f46d31f7607b75 (patch) | |
tree | 99aa7de39093fa08b8b531dc4454dede36bd72fb /tests/proc/bug_1268.v | |
parent | 4adcbecec5c6bfcdd3ed1d6ed753d3a7670e3eea (diff) | |
download | yosys-4a942ba7b9bb76f207adf23369f46d31f7607b75.tar.gz yosys-4a942ba7b9bb76f207adf23369f46d31f7607b75.tar.bz2 yosys-4a942ba7b9bb76f207adf23369f46d31f7607b75.zip |
proc_clean: fix order of switch insertion.
Fixes #1268.
Diffstat (limited to 'tests/proc/bug_1268.v')
-rw-r--r-- | tests/proc/bug_1268.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/proc/bug_1268.v b/tests/proc/bug_1268.v new file mode 100644 index 000000000..698ac937a --- /dev/null +++ b/tests/proc/bug_1268.v @@ -0,0 +1,23 @@ +module gold (input clock, ctrl, din, output reg dout); + always @(posedge clock) begin + if (1'b1) begin + if (1'b0) begin end else begin + dout <= 0; + end + if (ctrl) + dout <= din; + end + end +endmodule + +module gate (input clock, ctrl, din, output reg dout); + always @(posedge clock) begin + if (1'b1) begin + if (1'b0) begin end else begin + dout <= 0; + end + end + if (ctrl) + dout <= din; + end +endmodule |