Merge pull request #3502 from jix/equiv_opt_fixes

equiv_opt and clk2fflogic fixes

5 files changed, 19 insertions, 20 deletions

diff --git a/tests/opt/opt_dff_en.ys b/tests/opt/opt_dff_en.ys
index 06ee6c63d..9538afcc2 100644
--- a/tests/opt/opt_dff_en.ys
+++ b/tests/opt/opt_dff_en.ys
@@ -6,7 +6,7 @@ module top(...);
 
 input CLK;
 input [1:0] D;
-output [15:0] Q;
+output [11:0] Q;
 input SRST;
 input ARST;
 input [1:0] CLR;
diff --git a/tests/opt/opt_dff_mux.ys b/tests/opt/opt_dff_mux.ys
index ed01bed59..f21f9e9b8 100644
--- a/tests/opt/opt_dff_mux.ys
+++ b/tests/opt/opt_dff_mux.ys
@@ -7,7 +7,7 @@ module top(...);
 input CLK;
 input NE, NS;
 input EN;
-output [23:0] Q;
+output [17:0] Q;
 input [23:0] D;
 input SRST;
 input ARST;
diff --git a/tests/opt/opt_dff_qd.ys b/tests/opt/opt_dff_qd.ys
index afc96c42f..7b0b4c224 100644
--- a/tests/opt/opt_dff_qd.ys
+++ b/tests/opt/opt_dff_qd.ys
@@ -7,7 +7,7 @@ module top(...);
 input CLK;
 input EN;
 (* init = 24'h555555 *)
-output [23:0] Q;
+output [19:0] Q;
 input SRST;
 input ARST;
 input [1:0] CLR;
diff --git a/tests/opt/opt_dff_sr.ys b/tests/opt/opt_dff_sr.ys
index 0961cb11e..1d3fd300e 100644
--- a/tests/opt/opt_dff_sr.ys
+++ b/tests/opt/opt_dff_sr.ys
@@ -22,10 +22,9 @@ EOT
 
 design -save orig
 
-# Equivalence check will fail for unmapped adlatch and dlatchsr due to negative hold hack.
-#equiv_opt -undef -assert -multiclock opt_dff
-#design -load postopt
-opt_dff
+equiv_opt -undef -assert -multiclock opt_dff
+design -load postopt
+
 select -assert-count 1 t:$dffsr
 select -assert-count 1 t:$dffsr r:WIDTH=2 %i
 select -assert-count 1 t:$dffsre
@@ -36,9 +35,9 @@ select -assert-none t:$sr
 
 design -load orig
 
-#equiv_opt -undef -assert -multiclock opt_dff -keepdc
-#design -load postopt
-opt_dff -keepdc
+equiv_opt -undef -assert -multiclock opt_dff -keepdc
+design -load postopt
+
 select -assert-count 1 t:$dffsr
 select -assert-count 1 t:$dffsr r:WIDTH=4 %i
 select -assert-count 1 t:$dffsre
@@ -51,9 +50,9 @@ select -assert-count 1 t:$sr r:WIDTH=4 %i
 design -load orig
 simplemap
 
-#equiv_opt -undef -assert -multiclock opt_dff
-#design -load postopt
-opt_dff
+equiv_opt -undef -assert -multiclock opt_dff
+design -load postopt
+
 select -assert-count 1 t:$_DFF_PP0_
 select -assert-count 1 t:$_DFF_PP1_
 select -assert-count 1 t:$_DFFE_PN0P_
@@ -65,9 +64,9 @@ select -assert-none t:$_DFF_PP0_ t:$_DFF_PP1_ t:$_DFFE_PN0P_ t:$_DFFE_PN1P_ t:$_
 design -load orig
 simplemap
 
-#equiv_opt -undef -assert -multiclock opt_dff -keepdc
-#design -load postopt
-opt_dff -keepdc
+equiv_opt -undef -assert -multiclock opt_dff -keepdc
+design -load postopt
+
 select -assert-count 1 t:$_DFF_PP0_
 select -assert-count 1 t:$_DFF_PP1_
 select -assert-count 2 t:$_DFFSR_PPP_
diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys
index a879f3ec9..8874f2775 100644
--- a/tests/opt/opt_expr_xor.ys
+++ b/tests/opt/opt_expr_xor.ys
@@ -10,7 +10,7 @@ design -save read
 select -assert-count 2 t:$xor
 select -assert-count 2 t:$xnor
 
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-none t:$xor
 select -assert-none t:$xnor
@@ -19,7 +19,7 @@ select -assert-count 2 t:$not
 
 design -load read
 simplemap
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-none t:$_XOR_
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
@@ -34,7 +34,7 @@ $_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1]));
 endmodule
 EOT
 select -assert-count 2 t:$_XNOR_
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 design -load postopt
 select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_
 select -assert-count 1 t:$_NOT_
@@ -49,7 +49,7 @@ assign y = a~^1'b0;
 assign z = a~^1'b1;
 endmodule
 EOT
-equiv_opt opt_expr
+equiv_opt -assert opt_expr
 
 
 # Single-bit $xor