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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-24 14:38:03 +0200 |
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| committer | Kamil Rakoczy <krakoczy@antmicro.com> | 2020-06-24 14:46:21 +0200 |
| commit | f6d06c9f7b01641a657a9f69ef8ce9cb263ff47b (patch) | |
| tree | 16180c8599860a47babf9897a16349d0c69edb0a /tests/opt | |
| parent | a4b4c22c962e2971a093da9cf2364ec19050dd32 (diff) | |
| download | yosys-f6d06c9f7b01641a657a9f69ef8ce9cb263ff47b.tar.gz yosys-f6d06c9f7b01641a657a9f69ef8ce9cb263ff47b.tar.bz2 yosys-f6d06c9f7b01641a657a9f69ef8ce9cb263ff47b.zip | |
Add xor-assignment test
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/opt_expr_xor_assignment.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_xor_assignment.ys b/tests/opt/opt_expr_xor_assignment.ys new file mode 100644 index 000000000..924185e09 --- /dev/null +++ b/tests/opt/opt_expr_xor_assignment.ys @@ -0,0 +1,15 @@ +read_verilog -sv <<EOT +module opt_expr_xor_test(input [3:0] i, input [7:0] j, output [8:0] o); +wire[8:0] a = 8'b0; +initial begin + a ^= i; + a ^= j; +end + assign o = a; +endmodule +EOT +proc +equiv_opt -assert opt_expr -fine +design -load postopt + +select -assert-count 1 t:$xor r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=4 %i %i %i |