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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 21:58:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-21 21:58:20 -0700 |
| commit | bb1a8a019030022e8e5ad794691497c725ec86b2 (patch) | |
| tree | 4ce7a0979b95066515ef4d53b333c7d21db02181 /tests/opt | |
| parent | d3a212ff91de5e4f082f2c133becd4338661ac16 (diff) | |
| download | yosys-bb1a8a019030022e8e5ad794691497c725ec86b2.tar.gz yosys-bb1a8a019030022e8e5ad794691497c725ec86b2.tar.bz2 yosys-bb1a8a019030022e8e5ad794691497c725ec86b2.zip | |
Add test
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/opt_expr.ys | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index f0306efa1..4affc1ac8 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -221,3 +221,17 @@ check equiv_opt opt_expr -fine design -load postopt select -assert-count 1 t:$alu r:A_WIDTH=8 r:B_WIDTH=8 r:Y_WIDTH=9 %i %i %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_shiftx(input [2:0] a, input [1:0] b, output y); + \$shiftx #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(2), .Y_WIDTH(1)) shiftx (.A({1'bx,a}), .B(b), .Y(y)); +endmodule +EOT +check + +equiv_opt opt_expr +design -load postopt +select -assert-count 1 t:$shiftx r:A_WIDTH=3 %i |