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| author | Stefan Riesenberger <stefan.riesenberger@gmail.com> | 2022-11-05 10:05:08 +0100 |
|---|---|---|
| committer | myrtle <gatecat@ds0.me> | 2023-03-10 10:48:05 +0100 |
| commit | baa3659ea54aed3a714ed2fcb8b5242f5332ef37 (patch) | |
| tree | e94d17bf3b6d09628d87c54caa82aca4b2431b80 /tests/opt | |
| parent | b58664d441764b4de1d01c4efcdd45094ba71535 (diff) | |
| download | yosys-baa3659ea54aed3a714ed2fcb8b5242f5332ef37.tar.gz yosys-baa3659ea54aed3a714ed2fcb8b5242f5332ef37.tar.bz2 yosys-baa3659ea54aed3a714ed2fcb8b5242f5332ef37.zip | |
ice40: Fix path delay definitions
Parallel connections do not allow matching different bit widths.
A full connection has to be used instead.
Allows iverilog to parse the simulation library with hardware path delays enabled.
Diffstat (limited to 'tests/opt')
0 files changed, 0 insertions, 0 deletions