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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-12 22:37:44 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-04-13 16:52:22 +0200 |
| commit | 840bb170896c1acbbd321c4214df1f3b15108466 (patch) | |
| tree | 234ffc01b3af8bf3db9caefc216f2f621a369471 /tests/opt | |
| parent | 5448f9c85d61cf1b773fc5bf041264a46d354dfa (diff) | |
| download | yosys-840bb170896c1acbbd321c4214df1f3b15108466.tar.gz yosys-840bb170896c1acbbd321c4214df1f3b15108466.tar.bz2 yosys-840bb170896c1acbbd321c4214df1f3b15108466.zip | |
opt_expr: Optimize multiplications with low 0 bits in operands.
Fixes #1500.
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/opt_expr.ys | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/opt/opt_expr.ys b/tests/opt/opt_expr.ys index e0acead82..7c446afd1 100644 --- a/tests/opt/opt_expr.ys +++ b/tests/opt/opt_expr.ys @@ -291,3 +291,31 @@ check equiv_opt -assert opt_expr -keepdc design -load postopt select -assert-count 1 t:$shift r:A_WIDTH=13 %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_mul_low_bits(input [2:0] a, input [2:0] b, output [7:0] y); + \$mul #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(8)) mul (.A({a, 1'b0}), .B({b, 1'b0}), .Y(y)); +endmodule +EOT +check + +equiv_opt -assert opt_expr +design -load postopt +select -assert-count 1 t:$mul r:A_WIDTH=3 %i r:B_WIDTH=3 %i r:Y_WIDTH=6 %i + +########### + +design -reset +read_verilog -icells <<EOT +module opt_expr_mul_low_bits(input [2:0] a, input [2:0] b, output [7:0] y); + \$mul #(.A_SIGNED(0), .B_SIGNED(0), .A_WIDTH(4), .B_WIDTH(4), .Y_WIDTH(8)) mul (.A({a, 1'b0}), .B({b, 1'b0}), .Y(y)); +endmodule +EOT +check + +equiv_opt -assert opt_expr -keepdc +design -load postopt +select -assert-count 1 t:$mul r:A_WIDTH=4 %i r:B_WIDTH=4 %i r:Y_WIDTH=8 %i |