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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 21:20:42 +0200 |
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| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2022-05-18 22:48:55 +0200 |
| commit | 606f1637aeabe2b7ff31520a9f0d37899b5cb06b (patch) | |
| tree | d916ffcac9cd84022eea6ab83fe1e941251b819e /tests/opt | |
| parent | 982a11c709b4b363f85ae52a127f8a98bda30a3f (diff) | |
| download | yosys-606f1637aeabe2b7ff31520a9f0d37899b5cb06b.tar.gz yosys-606f1637aeabe2b7ff31520a9f0d37899b5cb06b.tar.bz2 yosys-606f1637aeabe2b7ff31520a9f0d37899b5cb06b.zip | |
Add memory_bmux2rom pass.
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/memory_bmux2rom.ys | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/tests/opt/memory_bmux2rom.ys b/tests/opt/memory_bmux2rom.ys new file mode 100644 index 000000000..039885965 --- /dev/null +++ b/tests/opt/memory_bmux2rom.ys @@ -0,0 +1,27 @@ +read_ilang << EOT + +module \top + wire width 4 input 0 \S + wire width 5 output 1 \Y + + cell $bmux $0 + parameter \WIDTH 5 + parameter \S_WIDTH 4 + connect \A 80'10110100011101110001110010001110101010111000110011111111111110100000110100111000 + connect \S \S + connect \Y \Y + end +end + +EOT + +hierarchy -auto-top + +design -save preopt +memory_bmux2rom +select -assert-count 1 t:$memrd_v2 +memory_map +opt_dff +design -stash postopt + +equiv_opt -assert -run prepare: dummy |