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author | Eddie Hung <eddie@fpgeh.com> | 2020-04-01 14:17:01 -0700 |
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committer | GitHub <noreply@github.com> | 2020-04-01 14:17:01 -0700 |
commit | 4ae7f3a8edded54c33a92b02659167c8a6af2522 (patch) | |
tree | 11da11fa2a7d05f7e45dfd6b3f011d5120edb846 /tests/opt | |
parent | e79bc45975321b806b23c47a41f2eb26c16f342e (diff) | |
parent | 0c0dc4ffc3c907fbe6973c925e9de07c2286cd6a (diff) | |
download | yosys-4ae7f3a8edded54c33a92b02659167c8a6af2522.tar.gz yosys-4ae7f3a8edded54c33a92b02659167c8a6af2522.tar.bz2 yosys-4ae7f3a8edded54c33a92b02659167c8a6af2522.zip |
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
Diffstat (limited to 'tests/opt')
-rw-r--r-- | tests/opt/opt_expr_xor.ys | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys new file mode 100644 index 000000000..21439fd53 --- /dev/null +++ b/tests/opt/opt_expr_xor.ys @@ -0,0 +1,52 @@ +read_verilog <<EOT +module top(input a, output [3:0] y); +assign y[0] = a^1'b0; +assign y[1] = 1'b1^a; +assign y[2] = a~^1'b0; +assign y[3] = 1'b1^~a; +endmodule +EOT +design -save read +select -assert-count 2 t:$xor +select -assert-count 2 t:$xnor + +equiv_opt opt_expr +design -load postopt +select -assert-none t:$xor +select -assert-none t:$xnor +select -assert-count 2 t:$not + + +design -load read +simplemap +equiv_opt opt_expr +design -load postopt +select -assert-none t:$_XOR_ +select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-count 3 t:$_NOT_ + + +design -reset +read_verilog -icells <<EOT +module top(input a, output [1:0] y); +$_XNOR_ u0(.A(a), .B(1'b0), .Y(y[0])); +$_XNOR_ u1(.A(1'b1), .B(a), .Y(y[1])); +endmodule +EOT +select -assert-count 2 t:$_XNOR_ +equiv_opt opt_expr +design -load postopt +select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ +select -assert-count 1 t:$_NOT_ + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] w, x, y, z); +assign w = a^1'b0; +assign x = a^1'b1; +assign y = a~^1'b0; +assign z = a~^1'b1; +endmodule +EOT +equiv_opt opt_expr |