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| author | David Shah <davey1576@gmail.com> | 2018-12-07 17:17:26 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-07 17:17:26 +0000 |
| commit | 435776120a40ed06ea42ca63bcca231913507ac3 (patch) | |
| tree | 1509de1bf1e0413a23f48aaf066a69ea9068cb8f /tests/opt | |
| parent | 7d1088afc453f57f0ecc0f55ac2c91fd72ad8f2e (diff) | |
| parent | 7ec740b7ad4ee4bc02e2564671e0153cdd08152f (diff) | |
| download | yosys-435776120a40ed06ea42ca63bcca231913507ac3.tar.gz yosys-435776120a40ed06ea42ca63bcca231913507ac3.tar.bz2 yosys-435776120a40ed06ea42ca63bcca231913507ac3.zip | |
Merge pull request #727 from whitequark/opt_lut
opt_lut: leave intact LUTs with cascade feeding module outputs
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/opt_lut_port.il | 18 | ||||
| -rw-r--r-- | tests/opt/opt_lut_port.ys | 2 |
2 files changed, 20 insertions, 0 deletions
diff --git a/tests/opt/opt_lut_port.il b/tests/opt/opt_lut_port.il new file mode 100644 index 000000000..7eb71890f --- /dev/null +++ b/tests/opt/opt_lut_port.il @@ -0,0 +1,18 @@ +module $1 + wire width 4 input 2 \_0_ + wire output 4 \_1_ + wire input 3 \_2_ + wire output 1 \o + cell $lut \_3_ + parameter \LUT 16'0011000000000011 + parameter \WIDTH 4 + connect \A { \_0_ [3] \o 2'00 } + connect \Y \_1_ + end + cell $lut \_4_ + parameter \LUT 4'0001 + parameter \WIDTH 4 + connect \A { 3'000 \_2_ } + connect \Y \o + end +end diff --git a/tests/opt/opt_lut_port.ys b/tests/opt/opt_lut_port.ys new file mode 100644 index 000000000..51dfd988b --- /dev/null +++ b/tests/opt/opt_lut_port.ys @@ -0,0 +1,2 @@ +read_ilang opt_lut_port.il +select -assert-count 2 t:$lut |