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| author | Clifford Wolf <clifford@clifford.at> | 2018-12-16 15:54:26 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-16 15:54:26 +0100 |
| commit | 2a681909dff173f63659d7c882137e53ad768ce8 (patch) | |
| tree | b0e51b09eb3ce4f1ad3e071b25bae4f43619f55e /tests/opt | |
| parent | a2154c1be0842541d04e2d9e0ebac9ccb3b472be (diff) | |
| parent | 7ff5a9db2d17c384260c2220c9205a7b4891f001 (diff) | |
| download | yosys-2a681909dff173f63659d7c882137e53ad768ce8.tar.gz yosys-2a681909dff173f63659d7c882137e53ad768ce8.tar.bz2 yosys-2a681909dff173f63659d7c882137e53ad768ce8.zip | |
Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/ice40_carry.v | 3 | ||||
| -rw-r--r-- | tests/opt/opt_lut.ys | 13 |
2 files changed, 1 insertions, 15 deletions
diff --git a/tests/opt/ice40_carry.v b/tests/opt/ice40_carry.v deleted file mode 100644 index ed938932a..000000000 --- a/tests/opt/ice40_carry.v +++ /dev/null @@ -1,3 +0,0 @@ -module SB_CARRY (output CO, input I0, I1, CI); - assign CO = (I0 && I1) || ((I0 || I1) && CI); -endmodule diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index 86ad93bb3..59b12c351 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,15 +1,4 @@ read_verilog opt_lut.v synth_ice40 ice40_unlut -design -save preopt - -opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 -design -stash postopt - -design -copy-from preopt -as preopt top -design -copy-from postopt -as postopt top -equiv_make preopt postopt equiv -techmap -map ice40_carry.v -prep -flatten -top equiv -equiv_induct -equiv_status -assert +equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 |