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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-20 13:44:21 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-06-20 13:44:21 +0200 |
| commit | 2454ad99bf49afe752d6fd1c1567f59ee9e26736 (patch) | |
| tree | f0994e4d7bcc9621b63d1e4cd07f2fe8134611a5 /tests/opt | |
| parent | 73bd1d59a7579ea74fb4a201771c983eeaf9a76a (diff) | |
| download | yosys-2454ad99bf49afe752d6fd1c1567f59ee9e26736.tar.gz yosys-2454ad99bf49afe752d6fd1c1567f59ee9e26736.tar.bz2 yosys-2454ad99bf49afe752d6fd1c1567f59ee9e26736.zip | |
Refactor "opt_rmdff -sat"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/opt_ff_sat.v | 25 | ||||
| -rw-r--r-- | tests/opt/opt_ff_sat.ys | 1 |
2 files changed, 12 insertions, 14 deletions
diff --git a/tests/opt/opt_ff_sat.v b/tests/opt/opt_ff_sat.v index fc1e61980..5a0a6fe37 100644 --- a/tests/opt/opt_ff_sat.v +++ b/tests/opt/opt_ff_sat.v @@ -1,15 +1,12 @@ -module top( - input clk, - input a, - output b - ); - reg b_reg; - initial begin - b_reg <= 0; - end - - assign b = b_reg; - always @(posedge clk) begin - b_reg <= a && b_reg; - end +module top ( + input clk, + output reg [7:0] cnt +); + initial cnt = 0; + always @(posedge clk) begin + if (cnt < 20) + cnt <= cnt + 1; + else + cnt <= 0; + end endmodule diff --git a/tests/opt/opt_ff_sat.ys b/tests/opt/opt_ff_sat.ys index 13e4ad29b..4e7cc6ca4 100644 --- a/tests/opt/opt_ff_sat.ys +++ b/tests/opt/opt_ff_sat.ys @@ -2,3 +2,4 @@ read_verilog opt_ff_sat.v prep -flatten opt_rmdff -sat synth +select -assert-count 5 t:$_DFF_P_ |