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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-17 17:13:17 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-17 17:26:36 +0200 |
| commit | 2b777bbda8ec46033244230e4e0d6bcea2822fa7 (patch) | |
| tree | 6a5c69662d04f1a8a37d0f8ea1cb5a642462e16c /tests/opt/opt_share_bug2335.ys | |
| parent | 9a4f420b4b8285bd05181b6988c35ce45e3c979a (diff) | |
| download | yosys-2b777bbda8ec46033244230e4e0d6bcea2822fa7.tar.gz yosys-2b777bbda8ec46033244230e4e0d6bcea2822fa7.tar.bz2 yosys-2b777bbda8ec46033244230e4e0d6bcea2822fa7.zip | |
opt_share: Refactor, fix some bugs.
Fixes #2334.
Fixes #2335.
Fixes #2336.
Diffstat (limited to 'tests/opt/opt_share_bug2335.ys')
| -rw-r--r-- | tests/opt/opt_share_bug2335.ys | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/tests/opt/opt_share_bug2335.ys b/tests/opt/opt_share_bug2335.ys new file mode 100644 index 000000000..0846a9ec3 --- /dev/null +++ b/tests/opt/opt_share_bug2335.ys @@ -0,0 +1,27 @@ +read_verilog <<EOT + +module top(...); + +input [3:0] A, B, C; +input S; +input [1:0] T; +output [3:0] X; +output reg [3:0] Y; + +wire [3:0] D = A + B; + +assign X = S ? D : A + C; +always @* begin + case(T) + 2'b01: Y <= A; + 2'b10: Y <= B; + default: Y <= D; + endcase +end + +endmodule + +EOT + +proc +equiv_opt -assert opt_share |